Many HPC applications are massively parallel and can benefit from the spatial parallelism offered by reconfigurable logic. While modern memory technologies can offer high bandwidth, designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. Addressing these challenges requires to combine optimizations that range from software to hardware design.

In this tutorial, we will give an overview of the challenges for generating massively parallel accelerators on FPGA for high-performance computing. We will also show how it is possible to combine compilers, source-to-source transformations, and commercial HLS tools for supporting the designer in the generation of high-performance memory architectures.

Stephanie Soldavini is a PhD student in the Department of Electronics, Informatics and Bioengineering at Politecnico di Milano in Milan, Italy. She received her BS/MS in Computer Engineering from Rochester Institute of Technology (RIT) in 2019. Her masters thesis was on reduced-graph based optimizations for scheduling in high-level synthesis. Her research focuses on automatic hardware generation with a focus on memory aspects.

Christian Pilato is a Tenure-Track Assistant Professor at Politecnico di Milano. He was a Post-doc Research Scientist at Columbia University (2013-2016) and at the ALaRI Institute of the Università della Svizzera italiana (2016-2018). He was also a Visiting Researcher at New York University, Delft University of Technology, and Chalmers University of Technology. He has a Ph.D. in Information Technology from Politecnico di Milano (2011). His research interests focus on the design, optimization, and prototyping of heterogeneous system-on-chip architectures and reconfigurable systems, with emphasis on memory and security aspects. Starting from October 2020, he is the Scientific Coordinator of the H2020 EVEREST project. He served as program chair of EUC 2014 and he will be program chair of ICCD 2022. He is currently serving in the program and organizing committees of many conferences on EDA, CAD, embedded systems, and reconfigurable architectures (DAC, ICCAD, DATE, CASES, FPL, ICCD, etc.) He is a Senior Member of IEEE and ACM, and a Member of HiPEAC.

This lab aims to provide students with the practical skills necessary to design advanced Self-* Cyber-Physical Systems (CPSs), with a specific focus on applications in CPS control and image processing. Participants will have the opportunity to engage in hands-on exercises using Programmable Systems-on-Chip and simulators. This practical approach will offer valuable experience to participants, boosting their confidence in tackling real-world challenges in CPS design. By the end of the lab, students will have gained strong practical skills in designing advanced adaptive CPSs and the ability to apply their knowledge in real-world situations. This lab presents an invaluable opportunity for those seeking to expand and complementing the more theoretical view provided in the previous talk on Evolvable Self-* Systems.

Andrés Otero is a Telecommunications Engineer from the University of Vigo, where he graduated with Honors in 2007. He completed a Master’s and Doctorate in Industrial Electronics from the Universidad Politécnica de Madrid (UPM) in 2009 and 2014, respectively. He also has a specialist degree in Signal Processing. Currently, he serves as an Associate Professor at UPM. His areas of interest are embedded and/or reconfigurable systems, evolutionary computation, and machine learning at the Edge. It can be highlighted his experience, both in the design and implementation of FPGA-based systems, and his background in evolvable (and neuroevolvable) hardware. As a result of this work, he is the co-author of 19 articles in JCR-indexed journals, such as Transactions on Computers, Internet of Things Journal, and IEEE Sensors. In addition, he has published two book chapters and more than 40 communications at conferences such as FPL, ReConFig, AHS, or ARC. He is the co-author of the best papers in the ReConFig 2012 and ARC 2020 conferences. Andrés Otero regularly participates in the program committee of some of these conferences, being ReCoSoC 2017 program Chair and FPL track program chair in 2021. His research work has been carried out within the framework of public-funded projects, both at Spanish (DR.SIMON, DREAMS, REBECCA, PLATINO, and TALENT) and European (SMART, ENABLE-S3, ENVIGUARD, FASTCUDA, CERBERO, KYKLOS4.0, InSecTT, and A-IQReady) levels

Alfonso Rodríguez has a MSc on Industrial Electronics (2014) and a PhD on Electrical and Electronics Engineering (2020), both by Universidad Politécnica de Madrid (UPM). Currently, he works as an Assistant Professor at UPM and carries out its research activity as a member of the Center of Industrial Electronics (CEI-UPM).His main research interests are high-performance embedded systems, reconfigurable computing, open computer architectures (e.g., RISC-V), and edge AI/ML. His work is backed by 9 publications in JCR-indexed journals, as well as by 17 conference publications, 1 book, and 1 book chapter. He has actively participated in projects of different nature, both European (ENABLE-S3, CERBERO, KYKLOS 4.0, A-IQ Ready) and Spanish (REBECCA, PLATINO, TALENT, COGNITION). He is part of the steering committee of the DASIP workshop, which he also co-chaired in 2023.

Large amounts of data are being collected thorough the new generation of digital medical devices, from diagnostic equipment to implantable devices. Increasingly, this data is being used to make decisions (such as diagnoses) on patients, and hence its security and privacy must be guaranteed. Often, Cyber-Physical Systems are used: for instance, an implantable automatic defibrillator, which makes an automatic decision to deliver an energy electric shock to the heart of someone who is in cardiac arrest. However, current security techniques have a high overhead, which makes them difficult to implement on constrained devices: the efficiency of the security techniques must therefore be increased, to enable the technology to be deployed more widely.

The EU-funded SECURED project aims to increase efficiency by scaling up multi-party computation, homomorphic encryption, data anonymisation, and private and unbiased AI, which are key security and privacy technique used on medical devices. In this tutorial, we will demonstrate how secure computation techniques including homomorphic encryption can be adopted in constrained settings, and applied to CPSs and medical devices. Students will be introduced to the basic of secure computation and will practice with state of the art libraries implementing the presented techniques.

Dr. Apostolos Fournaris is a Principal Researcher (Research Associate Professor) in Industrial Systems Institute of Research Center ATHENA. He has worked for the Information and Communication Technologies Lab in Sophia Antipolis Hitachi Europe SAS European R-D Centre for two years on Hardware Security and Trust research. He has acted as a visiting lecturer at Monash University, Australia for 2 year and as an adjunct Assistant Professor in the University of Patras and University of Peloponesse for more than 10 years. His main research interests are IoT, Edge Embedded System/Cyber-Physical system hardware and software security with focus on industrial and critical infrastructures, Implementation attacks and resistance techniques on hardware or Software implemented security systems (Microarchitectural attacks (Rowhammer, cache attacks), Side channel attacks, fault injection attacks, Hardware Trojans) and Cryptographic Engineering on Public Key, PostQuantum cryptography and Homomorphic Encryption. He has published more than 100 research articles in international conferences and journals on hardware security and trust, cryptographic engineering and industrial CPS research topics.

Paolo Palmieri is a Tenured Assistant Professor (Lecturer above the Bar) in Cyber Security at University College Cork, Ireland, and holds a PhD in Cryptography from the Université catholique de Louvain in Belgium. His research work focuses on cryptography, privacy and anonymity and his interests include secure computation, privacy-enhancing technologies, anonymity protocols and de-anonymization, location privacy and the security of smart cities and e-health. He is a Funded Investigator in two large national research centers (CONNECT and Insight), and his research has been supported by several grants from Science Foundation Ireland, Enterprise Ireland and the EU Horizon Europe program.

Dr. Francesco Regazzoni is a Tenured UD1 at the University of Amsterdam (Amsterdam, The Netherlands) and also affiliated with Università della Svizzera Italiana (Lugano, Switzerland). He received his Master of Science degree from Politecnico di Milano and his PhD degree at Università della Svizzera Italiana. He has been assistant researcher at the Université Catholique de Louvain and at Technical University of Delft, and visiting researcher at several institutions, including NEC Labs America, Ruhr University of Bochum, EPF Lausanne, and NTU Singapore. His research interests are mainly focused on embedded systems security, covering in particular side channel attacks, electronic design automation for security, hardware Trojans, and low energy cryptography. He has published more than 130 peer reviewed papers in the area of security and design automation, (including CHES, DAC, DATE, HOST, EUROCRYPT and ASIACRYPT) and has been in the technical program committed of top conferences of the area (including CHES, DAC, DATE, ICCAD, HOST, and COSADE). He is currently the coordinator of the SECURED Horizon project.