The presentation will focus on Placer: a tool that was developed in the TANGO H2020 project. Placer is a model-based tool that optimizes the mapping of task-based software onto heterogeneous hardware. It inputs two models: a model of the software that identifies tasks, their data dependencies and the various task implementations available for executing on different hardware, and a model of the hardware that describe various properties related to processing and I/O transfer capabilities. Placer then proposes an optimized mapping and scheduling of the software tasks onto the hardware. The mapping includes an assignment of tasks to processing elements (CPU Core, FPGA, etc. ) and a global schedule for initiating tasks and transmissions. Placer is also able to handle transmission delay and routing of transmissions on the available hardware buses. Tasks can have several implementations targeting different computing models, each suitable for a processing element (FPGA, CPU for instance). Tasks can even have several implementations targeting the same hardware and offering different trade-off’s between speed, memory usage etc. Subsequently, Placer also selects the most appropriate implementation for these tasks. Placer optimizes placement, schedule, and implementation selection in a single optimization process, so it can potentially reach a global optimum. Placer was developed based on the OscaR.cp constraint programming engine and is available open source.

Placer: a Design-time Model-based Tool for Mapping Task-based SW onto Heterogeneous HW