Modern cyber-physical systems (CPS) are increasingly adopting heterogeneous systems-on-chip (HeSoCs) as a computing platform to satisfy the demands of their sophisticated workloads. The capability of flexibly defining parallel, non-Von-Neumann processing logic and custom memory hierarchies, all within contained power envelopes, makes the FPGA an ideal candidate for acceleration. The main limiting factor in the adoption of FPGAs is the arduous development process.

In this tutorial, we present an innovative overlay that simplifies the adoption of Commercial-off-the-Shelf (COTS), FPGA-based HeSoCs coupling physical host CPU and DRAM with programmable logic (PL). The overlay is deployed on the PL of such HeSoCs and leverages open-source RISC-V soft-cores for flexible control of user-defined, application-specific accelerators. The development of these accelerators is, in turn, simplified by means of a dataflow-based approach (through the MDC tool), where the developer has to focus only on defining and connecting simple functionality blocks. Furthermore, this tool enables the implementation of coarse-grain reconfigurable accelerators, where more than one functionality can coexist in the same substrate. Finally, accelerator execution and accelerator reconfiguration can both be achieved via standard computation offloading from the host CPU to the soft-cores (e.g., OpenMP v4+).

Alessandro Capotondi is currently an Assistant Professor in the FIM Department of the Università di Modena e Reggio Emilia (IT). He received the Ph.D. degree in Electrical, Electronic, and Information Engineering from the University of Bologna, Italy, in 2016. His research interests focus on heterogeneous computing architectures, reconfigurable architecture, parallel programming models, and deep learning-based intelligence targeting edge, ultra-low-power computing SoC. His research work has resulted in more than 30 international conferences and journal publications.

Daniel Madroñal received his PhD (cum laude) at Universidad Politécnica de Madrid in 2020, defending the thesis entitled “Energy Consumption Reduction on High Performance Embedded Systems for Hyperspectral Imaging Cancer Detection”. He is currently a postdoctoral researcher at the University of Sassari, where his research focuses on code generation tools to automate the design for advanced reconfigurable hardware architectures using dataflow approaches. At the moment, his work revolves around the field of companion computers to perform real-time onboard processing on UAVs and UGVs employed in the context of smart and precision agriculture.

CPS operate in dynamic and resource-constrained environments. Application quality requirements vary, resource availability varies, resources are shared between applications. Active management of application qualities (such as latency, throughput) and resources (for instance, processing, bandwidth, storage) improves overall value and efficiency of CPS. Virtual platform solutions allow predictable sharing of resources by allocating resource budgets to application components. The lecture introduces a component-interface model to capture the trade-off capabilities between application qualities and resource budgets of (re)configurable CPS components. These trade-off relations are captured in a mathematical model suitable for multi-objective optimization. The component-interface models come with well-defined composition methods to build systems from components. The lecture then outlines a generic framework for active quality and resource management (QRM) based on the introduced component-interface models.

The tutorial introduces the participants to the Quality and Resource Modeling Language (QRML) and tools that support the QRM approach and component model. In small exercises, we experience hands-on how QRM component models can be expressed in a precise way, how they are composed to system models that precisely capture a system’s QRM trade-offs and how QRML models can be used to identify optimal configurations in an automated way with constraint-solving techniques.

Twan Basten received the M.Sc. and Ph.D. degrees in computing science from Eindhoven University of Technology (TU/e), Eindhoven, the Netherlands. He is currently a Professor with the Department of Electrical Engineering, TU/e. He is also a Senior Research Fellow with ESI, TNO, Eindhoven. His current research interests include the design of embedded and cyber-physical systems, model-driven performance engineering, and computational models. He is a senior member of IEEE and a life member of ACM.

Marc Geilen received the M.Sc. and Ph.D. degrees in electrical engineering from Eindhoven University of Technology (TU/e), Eindhoven, the Netherlands. He is currently an Associate Professor of model-based design methods for embedded and cyber-physical system with the Department of Electrical Engineering at TU/e. His research interests include model-based design processes, formal models-of-computation, embedded signal processing, multiprocessor systems, and multi-objective optimization and trade-off analysis.

Many HPC applications are massively parallel and can benefit from the spatial parallelism offered by reconfigurable logic. While modern memory technologies can offer high bandwidth, designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. Addressing these challenges requires to combine optimizations that range from software to hardware design.

In this tutorial, we will give an overview of the challenges for generating massively parallel accelerators on FPGA for high-performance computing. We will also show how it is possible to combine compilers, source-to-source transformations, and commercial HLS tools for supporting the designer in the generation of high-performance memory architectures.

Stephanie Soldavini is a PhD student in the Department of Electronics, Informatics and Bioengineering at Politecnico di Milano in Milan, Italy. She received her BS/MS in Computer Engineering from Rochester Institute of Technology (RIT) in 2019. Her masters thesis was on reduced-graph based optimizations for scheduling in high-level synthesis. Her research focuses on automatic hardware generation with a focus on memory aspects.

Christian Pilato is a Tenure-Track Assistant Professor at Politecnico di Milano. He was a Post-doc Research Scientist at Columbia University (2013-2016) and at the ALaRI Institute of the Università della Svizzera italiana (2016-2018). He was also a Visiting Researcher at New York University, Delft University of Technology, and Chalmers University of Technology. He has a Ph.D. in Information Technology from Politecnico di Milano (2011). His research interests focus on the design, optimization, and prototyping of heterogeneous system-on-chip architectures and reconfigurable systems, with emphasis on memory and security aspects. Starting from October 2020, he is the Scientific Coordinator of the H2020 EVEREST project. He served as program chair of EUC 2014 and he will be program chair of ICCD 2022. He is currently serving in the program and organizing committees of many conferences on EDA, CAD, embedded systems, and reconfigurable architectures (DAC, ICCAD, DATE, CASES, FPL, ICCD, etc.) He is a Senior Member of IEEE and ACM, and a Member of HiPEAC.